职位描述
芯片验证半导体ICDFT芯片设计芯片物理设计DV
岗位描述:
* Work with Architecture and Software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms
* Contribute significantly to verification infrastructure development
* Development of System Verilog/UVM based protocol/traffic generators/checkers, development of test plan based on functional requirements
岗位要求:
Masters degree desired, Bachelor's degree in CS/EE is required. 10+ years of relevant experience in ASIC verification field.
* Should have worked on developing/implementing test plans at the chip-level for complex ASICs.
* Fluent in System Verilog and scripting languages such as Python or Perl.
* Must have intimate knowledge of UVM methodology.
* Experience in the verification of SoC and other IPs such as CPU Subsystem, Ethernet, PCIE, DDR, Serdes etc.
* Knowledgeable about assertions and functional coverage
* Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
* Very good communication skills and ability and desire to work in a geographically diverse team environment.
* Will be responsible for definition, development and execution of self-checking tests for complex digital ASICs
SOC验证、CPU验证、GPGPU验证、DFT、芯片后端设计、芯片架构师等都有需求,要求3-15年经验。
工作地点:北京、上海、杭州、深圳、苏州、成都等
工作地址